Bare Die Assembly

Innovative, Cost-effective Packaging Techniques for Mid-volume Applications

Bare Die Packaging Technologies

ISI utilizes its expertise to effectively provide space-efficient solutions and high-performance circuit integration that optimize the electrical and mechanical properties of systems. ISI has demonstrated consistent success in designing and manufacturing modules with bare dies.

Next-Level Integration

ISI’s Next-Level Integration packaging blends high-density packaging with advanced interconnect capabilities to promptly afford miniaturized solutions. These packaging techniques include:

Typical Bare Die Packaging Methods

Multi-tier Wire Bond (PBGA) Package

Flip Chip (FC-PBGA) Package

IC Packaging

Once produced, bare die can be assembled by attaching it to a substrate or “packaged” through different processes. ISI has qualified a variety of stacked bare die techniques. These processes are available for use with standard die and do not require custom die or through-silicon vias (TSV). Below are the various die-stacking methods offered for bare die assembly.

3D Stacked Die

Same size die stacked with spacers
Flip Chip + Tiered "Wedding Cake"
Center bond using Z-controlled die attach
Tiered "Wedding Cake"

3D Substrate Stacking

Stacked substrates using bare die

Hybrid Packaging

Bare die packaged with other components

Applications

End-to-End Microelectronic Development Expertise

Ultra-dense, SWaP-optimized microelectronic assemblies. 

Survive harsh environments;
Temperature cycle, shock, and vibration.

Integration of sensors with microelectronic modules.

Multi-component modules in standard IC form factor
(BGA, QFP, etc.).

Replace obsolete ICs with a form/fit/function equivalent module.

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